In recent years, there has been a great use of various delay architectures for delaying digital signals in integrated circuit (IC) devices. Many clock alignment circuits have been included in the IC devices to provide internal on-chip clocks that are aligned in phase with an external system clock. For example, digital delay locked loops (DLL's) for clock alignment are commonly used in some IC devices (such as a CMOS) which have stringent timing requirements in a high speed memory system.
Digital DLL's are characterized by their use of a digital delay line (a digital delay circuit) and are typically made from simple digital circuit elements such as inverters, multiplexers and the like. The delay line (delay circuit) is a core part of a DLL, which has a number of delay cells connected in series. Typically, the last cell in the delay line connects to a node designated to be a clock output of the DLL. One or more delay cells may receive an external clock signal. After the external clock signal enters in the delay line, each delay cell passes the clock signal to achieve a proper adjusted clock signal.
There are various architectures to construct delay circuits. One of delay circuit architectures may use digital delay cells comprising inverters or buffers with multiplexers. For example, FIG. 1A shows a typical architecture of delay circuits comprising inverters and multiplexers. A problem with the conventional delay circuit is matching between delay cells (inverter or buffer) and multiplexers. Since an inverter and a multiplexer are two different types of architecture, the inverter's delay and the multiplexers' delay are different and therefore hard to match. In such case, overall delay of the delay circuit is not linear so that the design of the delay circuit becomes more complicated. Another problem with the conventional delay circuit may be an intrinsic delay in the delay circuit. The intrinsic delay (the delay which the delay circuit starts with) is too big to make the delay circuit usable in applications where small intrinsic delay is required. To overcome the intrinsic delay problem, dummy multiplexers are added to data bits to cancel out intrinsic delay in addition to the clock side. For example, FIG. 1B shows a typical architecture of a data side delay comprising dummy multiplexers. However, this approach may waste IC chip space and also create great complexity in designing IC chips.
Therefore, it would be desirable to provide a digital delay circuit with a small intrinsic delay suitable for an IC device with stringent timing requirements, which is simple to implement, fully scaleable and linear.